Resume

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• Bachelor of Applied Science in Electrical Engineering
  University of British Columbia
  Sep 2022 - May 2027

• ASIC Digital Design/Verification Intern
  Synopsys, Inc.
  Jan 2025 - Current
  
  • Designed and verified features within 224G Ethernet PHY IP transmitter and receiver blocks
  • Utilized PrimeTime and PrimePower for power estimation and generating power waveforms
  • Implemented VC SpyGlass LINT flows to improve RTL quality and identify design issues
  • Developed UVM testbenches for generating and verifying ATE test vectors through JTAG and APB
    
    
• Undergraduate Teaching Assistant I
  University of British Columbia
  Sep 2023 - Dec 2023, Sep 2024 - Dec 2024
  
  • 2024W1 ELEC 202 - Circuit Analysis II
  • 2024W1 CPSC 259 - Data Structures and Algorithms for Electrical Engineers
  • 2024W1, 2023W1 APSC 160 - Introduction to Computation in Engineering Design
    
    

• Electrical Team Lead
  UBC Sailbot
  Mar 2024 - Dec 2024
  • Undergraduate student team focused on creating fully autonomous sailboats capable of sailing in the Pacific Ocean and collecting research data for climate change research
  • Leading the electrical team consisting of more than 25 students in creating custom PCBs, firmware, motor systems, battery systems, and solar panel solutions
    
    
• Electrical Team Communication Systems Project Lead
  UBC Sailbot
  Aug 2023 - Mar 2024
  
  
• Electrical Team Member
  UBC Sailbot
  Sep 2022 - Aug 2023

• Waveform Generator and Music Player
  Jun 2024
  
  • A GUI application running on NIOS II CPU that is written in C, SystemVerilog, and VHDL that serves as a music player and a waveform generator with various modulations at the same time
    
  • See in Portfolio page
    
    
• RC4 Decoder
  Jun 2024
  
  • Decodes RC4-encrypted 32 byte messages with a 24-bit secret key within 1 second using a 64-core hardware accelerator written with VHDL and SystemVerilog for the DE1-SoC
    
  • See in Portfolio page
    
    
• Simple RISC CPU
  Dec 2023
  
  • A RISC CPU written in SystemVerilog based on a custom architecture that can run up to 119 MHz
    
  • Ranked 5th among 315 students and achieved a 2.006 geometric mean speedup compared to the reference CPU